[Micron HBM Expert: AI Computing Power Accelerates Faster Than HBM, Memory Wall Issue Worsens] According to a report by Jinse Finance, 'The memory wall still exists, and the situation may even be worsening.' Ragu Sriramaneni, an expert in HBM design architecture at Micron, expressed this view on the 23rd local time at the Hot Chips 2026 semiconductor academic conference held at Stanford University in the United States. The memory wall refers to the performance bottleneck caused when the processing speed of chips responsible for computation increases rapidly, but the memory responsible for data transmission cannot keep up. In the era of artificial intelligence, this bottleneck has not only persisted but has become increasingly severe. Sriramaneni stated that the computational performance of AI accelerators improves approximately threefold every two years, while the performance of HBM (High Bandwidth Memory), which handles data supply, has increased by less than twofold over the same period. Even with chips boasting powerful computational capabilities, if the data transmission channels are narrow, the ultimate performance will still be constrained by the speed of those channels. He predicted: 'Breaking the boundary between computational units and memory, with entirely new architectural designs, could be a path to overcoming the memory wall.'