**[Google Reportedly Collaborates with AMD to Design Next-Gen TPU, CPU Core IP Becomes Key, AI's Future May Rely More on CPU-Intensive Computing]** BlockBeats News, August 17: According to a SemiAnalysis client report citing market sources, Google is working with AMD to develop a product within its 10th-generation TPU lineup. This marks AMD's first significant involvement in a custom AI ASIC project. Analysts believe that while Google has nine generations of TPU development experience and has traditionally relied on Broadcom for actual silicon design, AMD's involvement is not necessary for conventional TPU designs. The core appeal of this collaboration lies in AMD's CPU IP, advanced packaging, and interconnect technologies. The report specifically highlights that Google and its clients are pushing for the integration of CPU cores within TPU packages to address the demands of reinforcement learning and other CPU-intensive workloads. While traditional LLM training remains accelerator-focused, inference and reinforcement learning for agent-based models require more general-purpose computing resources to operate alongside accelerators. This trend has already surfaced in Google's recent hardware configurations. For inference and reinforcement learning workloads, the TPU v8i system pairs every two TPUs with one Google Axion CPU, whereas the 7th-generation TPU servers paired one Intel Xeon processor with every four TPUs. Some sources suggest that in certain scenarios, a 1:1 ratio of CPUs to accelerators is the optimal configuration, implying that the future of AI computing may rely on CPUs far more than the market currently anticipates. If the collaboration with AMD materializes, Google could combine its in-house TPU accelerators with AMD's general-purpose computing cores to create a hybrid AI ASIC, potentially reshaping the competitive landscape of data center chips. [Original Link]