Author: hoidya｜𝟎𝐱𝐔

1/ What is the storage industry?

The storage industry is primarily composed of three core products: DRAM, NAND, and HBM. Together, they form the data memory system for all digital devices. Whether it is a mobile phone, computer, or data center, this layer of infrastructure must be relied upon for temporary data processing and long-term storage.

From a system architecture perspective, the storage industry is not a component independent of the computing system but rather a foundational dependency layer for all computing systems. Any computing task must first "read data," then "compute," and finally "write back results." Therefore, storage is one of the fundamental constraints in the computing process, rather than an optional module.

In the past two decades, the demand for this industry primarily came from three sources: consumer electronics (mobile phones and PCs), enterprise servers, and internet infrastructure. These demands share common characteristics: high dispersion, delayed renewal cycles, and limited scale of single-point demand. Thus, the market has long classified it as a typical cyclical semiconductor industry.

2/ Why has storage been seen as a cyclical industry for a long time?

When demand rises, prices increase rapidly, prompting manufacturers to expand production. However, as capacity construction cycles usually range from 12 to 24 months, the new supply often concentrates on release after the demand inflection point, leading to a rapid price decline. This mechanism forms a typical boom-bust cycle.

3/ What was the demand structure like before AI?

In this structure, storage, as a standardized product, is primarily priced based on supply-demand relationships rather than the long-term locked demand of a single large customer. Therefore, the market has a high spot attribute, allowing price signals to quickly reflect inventory changes and capacity adjustments.

4/ Why has AI fundamentally changed the storage demand structure? (From cyclical goods to infrastructure)

More critically, there have been changes on the supply side: since HBM profitability is significantly higher than traditional DRAM, manufacturers are proactively reallocating capacity, shifting wafers from DDR4/DDR5 production to HBM production. This structural squeezing effect causes traditional DRAM and NAND to experience "non-demand-driven shortages."

5/ How was storage priced in the past?

Prices are driven by inventory cycles, rather than demand structure.

The core constraint of this mechanism is the "lag of capacity construction (1-2 years) + demand deferrability."

However, this mechanism has been disrupted in the AI era, due to the simultaneous changes in two variables:

• First, demand has shifted from dispersed consumption to centralized procurement.
• Second, supply has shifted from "free market expansion" to "profit-priority allocation (HBM prioritized)."

6/ What structural changes are currently happening?

This structural adjustment has led to two results:

• First, traditional DRAM supply is contracting.
• Second, NAND is entering a state of passive shortage.

More extreme signals are coming from the delivery side: industry lead times have already extended from a normal 8-12 weeks to 39-52 weeks, with some automotive-grade memory even exceeding 70 weeks.

Price increases → manufacturers reduce spot supply → buyers lock in orders early → further reduce spot liquidity → prices continue to rise.

7/ Who benefits from this structure?

First layer: Supply side (Samsung / SK hynix / Micron)

These companies lock in future supplies through long-term contracts, essentially performing "time arbitrage": using current capital expenditures to secure future AI computing power and memory costs.

They find themselves between cash flow pressures and computing power needs, forming a closed loop through financing → capex → re-locking supply.

8/ Risks and conditions for falsification

Second, if the HBM technology path is replaced (for example, with new memory architectures or compute-memory fusion), the current HBM premium will be compressed, leading to a reflow of capacity back to DRAM/NAND.

In other words, the premise for this structure to hold is:

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